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10/13 10/8 OS作業
名稱	10/8 OS作業
日期	10/13
課程名稱	作業系統
指導教師	劉艾華

1.
Give two reasons why caches are useful.
What problems do they solve?
What problems do they cause?
If a cache can be made as large as the device for which it is caching
(for instance, a cache as large as a disk), why not make it that large and eliminate the device?

Caches are useful when two or more components need to ex-change data, and the components perform transfers at differing speeds. Caches solve the transfer problem by providing a buffer of intermediate speed between the components. If the fast device finds the data it needs in the cache, it need not wait for the slower device. The data in the cache must be kept consistent with the data in the components. If a component has a data value change, and the datum is also in the cache, the cache must also be updated. This is especially a problem on multiprocessor systems where more than one process may be accessing a datum.
A component may be eliminated by an equal-sized cache, but only if:
(1) the cache and the component have equivalent state-saving capacity (that is, if the component retains its data when electricity is removed, the cache must retain data as well),
and
(2) the cache is affordable, because faster storage tends to be more expensive.

2.
What Is the purpose of interrupts? What are the differences between a trap and an interrupt?
Can traps be generated intentionally by a user program?
If so, for what purpose?
An interrupt is a hardware-generated change-of-flow within the system. An interrupt handler is summoned to deal with the cause of the interrupt; control is then returned to the interrupted context and instruction. A trap is a software-generated interrupt. An interrupt can be used to signal the completion of an I/O to obviate the need for device pooling. A trap can be used to call operating system routines or to catch arithmetic errors.

3.
Please tell the functional differences between CPU and device controller.
Is there any similarity between them?
1.Difference:
CPU starts an I/O operation, and
continuously polls (checks) that device
until the I/O operation finishes
Device controller contains registers for
communication with that device
n Input register, output register — for data
n Control register — to tell it what to do
n Status register — to see what it’s done
2.Similarity:
CPU and device controllers all use a
common bus for communication
4.
Please discuss, in your own words, the cycle of the handling of an interrupt.
the exact source of the interrupt can be identified at hardware level.
1.A device asserts the interrupt signal at a hardwired interrupt level.
2.The processor registers the interrupt and waits to finish the current instruction execution.
3.Once the current instruction execution is completed, the processor initiates the interrupt handling by saving the current register contents on the stack.
4.The processor then switches to supervisor mode and initiates an interrupt acknowledge cycle.
5.The interrupting device responds to the interrupt acknowledge cycle with the vector number for the interrupt.
6.Processor uses the vector number obtained above and fetches the vector.
7.The address found at the vector is the address of the interrupt service routine (ISR) for the interrupting device.
8.After the ISR routine has performed its job, the ISR executes the "return from interrupt" instruction.
9.Execution of the "return from interrupt" instruction results in restoring the processor state. The processor is restored back to user mode.
Interrupt Handler
Setps in simple words:
1. Stop the running process.
2. Save the status of the process.
3. OS will search Interrupt vector according to Interrupt ID。
4. Get ISR（Interrupt Service Routine）original address.
5. Execute ISR.
6. After Executing ISR, go back to the status before stopping the process.

更新日期：2015/10/13 下午 05:53:06