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10/15/2015 10/08 OS 作業
名稱	10/08 OS 作業
日期	10/15/2015
課程名稱	作業系統
指導教師	劉艾華

1. Caches are useful when two or more components need to exchange data, and the components perform transfers at differing speeds. Caches solve the transfer problem by providing a buffer of intermediate speed between the components. If the fast device finds the data it needs in the cache, it doesn’t need to wait for slower device. The data in cache must be kept consistent with the data in the components. When a component has data value change, and the datum is also in the cache, the cache must also be updated. This is especially a problem or multiprocessor systems where more than one process may be accessing a datum.
A component may be eliminated by an equal sized cache but only if:
[a]. The cache and component have an equivalent state of saving capacity, if the component retains its data when electricity is removed, the cache must retain the data as well.
[b]. the cache is affordable, because the faster storage tends to be more extravagant.

2. The purpose of interrupts is to alter the flow of execution in response to some event. An interrupt is trigger in hardware while trap is trigger in software. User programs can generate traps intentionally. They may want to interact with some input or output which requires a system call.
3. A device controller is a part of a computer system that makes senses of the signals going to and coming from the CPU. The device controller receives the data from a connected device and stores it temporarily in some special purpose registers, for example local buffer inside the controller, then it communicates the data with a device driver.
4. The cycle of handling an interrupt is as below:
A device asserts the interrupts signal at hardwired interrupt level. The processor registers the interrupt and waits to finish the current instruction execution. Once the current instruction execution is completed the processor initiates the interrupts handling by saving the current register contents on the stack.
The processor then switches to supervisor mode and initiates an interrupts acknowledge cycle. No device responds to the interrupt acknowledge cycle, so the processor fetches he vector corresponding to the interrupt level. The address found at the vector is the address of the interrupt service routine (ISR).
The ISR polls all the devices to find the device that caused the interrupt. This is accomplished by checking the interrupt status register on the devices that could trigger the interrupt. Once the device is located, control is transfer to the handler specific to the interrupting device. After device specific ISR routine has performed its job, The ISR executes the “return form interrupt” instruction. Execution of the “return from interrupt” instruction results in restoring the processor state. The processor is restored back to user mode.

更新日期：2015/10/15 上午 12:44:45