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10.14 10/8 OS作業
名稱	10/8 OS作業
日期	10.14
課程名稱	作業系
指導教師	劉艾華

1. Caches are useful when two or more components need to ex-change data, and the components perform transfers at differing speeds. Caches solve the transfer problem by providing a buffer of intermediate speed between the components. If the fast device finds the data it needs in the cache, it need not wait for the slower device. The data in the cache must be kept consistent with the data in the components. If a component has a data value change, and the datum is also in the cache, the cache must also be updated. This is especially a problem on multiprocessor systems where more than one process may be accessing a datum.
A component may be eliminated by an equal-sized cache, but only if:
(a) the cache and the component have equivalent state-saving capacity (that is, if the component retains its data when electricity is removed, the cache must retain data as well),
and
(b) the cache is affordable, because faster storage tends to be more expensive.
2. The purpose of interrupts is to alter the flow of execution in response to some event. An interrupt is triggered in hardware and a trap is triggered in software. User programs can generate traps intentionally. They may want to interact with some I/O which requires a system call.
3. CPU and device controllers all use a common bus for communication
A device controller is a part of a computer system that makes sense of the signals going to, and coming from the CPU.
4. It saves the CPU state and invokes the appropriate interrupt handler using the interrupt vector (addresses of OS routines to handle various events).Handler must save and restore software state (e.g., registers it will modify),and CPU restores CPU state

更新日期：2015/10/23 下午 02:01:13